Since the invention of the integrated circuit, the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvement in lithography has resulted in considerable improvement in 2D integrated circuit formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required. An additional limit comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase.
Three-dimensional (3D) integrated circuits (ICs) are therefore created to resolve the above-discussed limitations. In a typical formation process of 3D IC, a plurality of wafers, each including an integrated circuit, are formed. The wafers are then bonded with the devices aligned. Much higher device density has been achieved using 3D IC technology. Accordingly, 3D IC technology has the potential of being the mainstream technology of the next generation.
Through-substrate vias (TSV) are formed to interconnect devices on the substrates of wafers. Up to six layers of wafers have been bonded in current practices while more may be following. For a plurality of layers of wafers of a 3DIC, the middle layers are called interlayers, which lie between a top layer and a bottom layer of the 3DIC. Each layer of a 3DIC typically contains a chip of that layer.
Other technologies for 3D IC exist too, such as Die-on-Wafer and Die-on-die. For Die-on-Wafer technology, electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dies are aligned and bonded onto die sites of the second wafer. An advantageous feature of the die-to-wafer bonding is that the size of dies may be smaller than the size of chips on the wafer. During a typical die-to-wafer bonding process, spaces will be left between the dies. The spaces are typically filled with a coating, such as spin-on-glass. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional dies may be added to the stacks before dicing. For Die-on-Die technology, electronic components are built on multiple dies, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding.
Automatic Test Equipment (ATE), or testers are used in the process of automatically testing the electrical characteristics and performance of finished devices known as the Device Under Test (DUT). ATEs can be applied to 3DICs where the DUT is a 3DIC. In general, an ATE consists of an elaborate controller or microprocessor-based system that controls: 1) boards or modules that can supply electrical excitation to the device under test (DUT) and 2) boards or modules that can measure the electrical characteristics and behavior of the DUT in response to the applied excitation.
Force-sense is a measurement technique wherein a power (voltage or current) is forced at a point in the circuit, or a test pad, and the resulting power (voltage or current) is measured at the same point. Force is to apply a specific stimulus to a DUT pin, while sense is to measure the resulting current or voltage. A sensing path or a channel is a single testing path dedicated by an automatic test equipment to one device-under-test (DUT) pin so that the power applied to the DUT pin goes through a functional path inside the DUT and is sensed at a pin by the sensor of the ATE.
There are various forms of testing. Diagnostic tests are tests performed to check if a system is malfunctioning and if so, to determine the possible cause(s) of the malfunction and the corresponding repair strategy. Functional testing on the other hand is the process of testing a device for its ability to perform its intended function.
An ATE can be a complicated system capable of automatically testing and diagnosing faults in sophisticated electronic packaged parts or on wafer testing, including system-on-chips and integrated circuits. An ATE can perform functional testing as well.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments, are simplified for explanatory purposes, and are not drawn to scale.